The present invention relates generally to voltage-to-frequency converters, and in particular to a methods and apparatuses for providing multi-channel capability in a synchronous voltage-to-frequency converter realized in an integrated circuit.
Several types of precision sensor systems are known that provide an analog signal output. In order to provide useful information to modem digital systems, the analog signal output of these precision sensors must be translated to digital format. Furthermore, many applications require the translation from analog to digital to be accomplished without loss of data during the conversion sequence. Typical applications requiring a xe2x80x9cno-lossxe2x80x9d conversion include, but are not limited to, Inertial Guidance and Navigation systems, Inertial Pointing Systems, and steering and attitude determination systems. Common successive approximation (SA) analog-to-digital converters (ADC) operate using a xe2x80x9choldxe2x80x9d time, which is not compatible with such a no-loss conversion.
Analog to digital conversion without loss of signal during conversion also accommodates digital filtering techniques, such as averaging over multiple samples, wherein quantization errors are reduced much faster, i.e., by 1/N rather than 1/{square root over (N)}, where: N is the number of samples used in averaging.
Voltage-To-Frequency Converters (VFC""s) are a form of ADC that provide no-loss conversion. Different VFC""s use different approaches to convert the analog signal directly into a frequency proportional to the signal. This frequency is then counted by electronic counter means, usually in a processing or control system, to complete the digital output.
A synchronous VFC or SVFC is a form of VFC that is available for precision systems. Typically, the SVFC utilizes an external clock to synchronize the frequency output. The SVFC is more precise than the VFC because the counting method of the frequency is synchronized to the input clock of the VFC, which eliminates any errors on the counted digital output due to clock aging or other clock error effects. Any clocking error that does occur is a common mode error between the VFC and the counting electronics. This type of error is normally eliminated in the conversion process. Unfortunately, most available SVFC devices available have limited capability such that they can only handle one channel of analog conversion. Additionally, the available SVFC integrated devices typically consume large amount of power relative to the power consumption desired of a semiconductor circuit.
The present invention provides a synchronous voltage-to-frequency converter that overcomes the limitations of the prior art by providing a multi-channel capability in a synchronous voltage-to-frequency converter realized in an integrated semiconductor circuit that minimizes power consumption.
According to one aspect of the invention, the multi-channel synchronous voltage-to-frequency converter includes an integrator operational amplifier adapted to receive both an analog data signal to be converted and a reset signal, the integrator operational amplifier being structured to integrate the sum of the analog signal and the reset signal and to generate an output signal as a function of the integrated sum; a comparator coupled to receive the output signal of the integrator and a reference level signal, the comparator being structured to output a logic level signal as a function of the received reference level signal; a digital logic circuit responsive to an external clock signal, the digital logic circuit coupled to receive the logic level signal and being structured to generate a reset control signal and a frequency output pulse as a function of the logic level signal; and a reset source switch coupled to receive the reset control signal and being structured to output the reset signal as a function of the reset control signal.
According to another aspect of the invention, the multi-channel synchronous voltage-to-frequency converter may also include a trimming circuit coupled to an input of the integrator that is adapted to receive both an analog data signal to be converted and a reference voltage for trimming the analog data signal.
According to another aspect of the invention, the multi-channel synchronous voltage-to-frequency converter may also include a clock phasing circuit adapted to receive the external clock signal and to output the clock signal controlling the digital logic circuit, the clock phasing circuit being structured to phase a plurality of frequency output pulses generated by the digital logic circuit as a function of the number of channels of the multi-channel SVFC circuit. The clock phasing circuit may be a digital divider and phase shifter circuit.
According to another aspect of the invention, the multi-channel synchronous voltage-to-frequency converter may also include a self-test circuit coupled to an input to a summing junction of the operational amplifier between the summing junction and analog data signal to be converted. The self-test circuit may be implemented as a MOSFET switch structured to present an essentially zero impedance path for the analog data signal to be converted.